As a solid-state imaging device (image sensor) using a photoelectric conversion element which detects light and generates an electric charge, a CMOS (complementary metal oxide semiconductor) image sensor has been put into practical use. A CMOS image sensor has been widely applied as part of various types of electronic apparatuses such as digital cameras, video cameras, monitoring cameras, medical endoscopes, personal computers (PC), and mobile phones and other portable terminals (mobile devices).
A CMOS image sensor has a floating diffusion (FD) amplifier having, for each pixel, a photodiode (photoelectric conversion element) and floating diffusion layer. For readout, the mainstream type is the column parallel output type that performs selects a certain row in a pixel array and simultaneously reads the pixels out to a column output direction.
In this regard, as the configuration of the pixel, as representative types, a first pixel configuration shown in FIG. 1, a second pixel configuration shown in FIG. 2, and a third pixel configuration shown in FIG. 3 can be illustrated.
FIG. 1 is a diagram showing an example of the first pixel configuration of a CMOS image sensor. FIG. 1 illustrates a 4-transistor (4Tr) APS pixel (for example, see PLT 1).
This 4TrAPS pixel 1 has one transfer transistor Tr1 as a transfer element, reset transistor Tr2 as a reset element, source-follower transistor Tr3 as a source-follower element, and selection transistor Tr4 as a selection element with respect to one photodiode (photoelectric conversion element) PD1.
The transfer transistor Tr1 is selected and becomes a conductive state for a predetermined transfer period and transfers a charge (electrons) which is photoelectrically converted and accumulated in the photodiode PD1 to the floating diffusion FD. The reset transistor Tr2 is selected and becomes a conductive state for a predetermined reset period and resets the floating diffusion FD to the potential of the power supply line. The selection transistor Tr4 is selected and becomes a conductive state at the time of readout scanning. Due to this, the source-follower transistor Tr3 outputs a readout signal of column output obtained by converting the charge in the floating diffusion FD to a voltage signal in accordance with the charge quantity (potential) to a vertical signal line LSGN1.
For example, in the readout scan period, after the floating diffusion FD is reset to the potential of the power supply line in the reset period, the charge in the floating diffusion FD is converted to a voltage signal in accordance with the charge quantity (potential) by the source-follower transistor Tr3 and is output as a readout reset voltage Vrst to the vertical signal line LSGN1. Then, in a predetermined transfer period, the charge (electrons) which is photoelectrically converted and accumulated in the photodiode PD1 is transferred to the floating diffusion FD. Then, by the source-follower transistor Tr3 and a capacitance Cfd1 parasitic on the floating diffusion FD, the charge in the floating diffusion FD is converted to the voltage signal in accordance with the charge quantity (potential) and output as a readout signal voltage Vsig to the vertical signal line LSGN1. The output signal of the pixel is processed as a differential signal (Vrst-Vsig).
In general, increased sensitivity of the pixel 1 in FIG. 1 can be realized by raising a conversion gain. In the pixel 1 in FIG. 1, a certain extent of increased sensitivity is possible by lowering the capacitance Cfd1 of the floating diffusion FD.
FIG. 2 is a diagram showing an example of the second pixel configuration of the CMOS image sensor. FIG. 2 shows an example of a capacitive trans-impedance amplifier (CTIA) pixel (for example see PLT 2 and PLT 3).
This CTIA pixel 2 has one reset transistor Tr11, driver transistor Tr12, auxiliary driver transistor Tr13, and feedback capacitor C1 with respect to one photodiode (photoelectric conversion element) PD2. The pixel 2 is connected through a selection transistor Tr14 to a vertical signal line LSGN2, while the vertical signal line LSGN2 is connected through P-channel transistors Tr15 and Tr16 to the power supply VDD.
In this pixel 2, increased sensitivity can be realized by making the capacitance Cfb1 of the feedback capacitor C1 smaller than the capacitance Cfd1 of the floating diffusion FD (sometimes simply referred to as an “FD”) of the pixel 1 in FIG. 1, so a low luminance subject can be brightly captured.
FIG. 3 is a diagram showing an example of the third pixel configuration of the CMOS image sensor. FIG. 3 shows an example of a pixel provided with a lateral overflow integration capacitor (LOFIC) C2 (capacitance Clofic) (for example, see PLT 4).
The pixel 3 in this FIG. 3 is comprised of the configuration of the pixel 1 in FIG. 1 to which an integration capacitor C2 connected to a switch transistor Tr5 and node LO is added.
In the pixel 3 in FIG. 3, an oversaturated charge overflowing from the photodiode PD1 in the same exposure time is not disposed of, but is integrated (accumulated) in the storage capacitor C2 having the capacitance Clofic.
The pixel 3 in FIG. 3 can have two types of conversion gain of the conversion gain due to the capacitance Cfd1 of the floating diffusion FD (high gain side:proportional to 1/Cfd1) and the conversion gain due to the capacitance Cfd1 of the floating diffusion FD+LOFIC capacitance Clofic of the integration capacitor C2 (low gain side: proportional to 1/(Cfd1+Clofic)).